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翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク Mill CPU Architecture ： ウィキペディア英語版 Mill CPU Architecture The Mill CPU architecture is a novel belt machine-based architecture for general purpose computing, which has been under development by Ivan Godard and his startup Mill Computing, Inc. (East Palo Alto, California;〔http://investing.businessweek.com/research/stocks/private/snapshot.asp?privcapId=261967066〕 formerly Out Of The Box Computing) since ca. 2003. Mill Computing claims it has a "10x single-thread power/performance gain over conventional out-of-order superscalar architectures" but "runs the same programs, without rewrite". Mill computing was founded by persons who formerly worked together on a family of DSP CPUs, the Phillips Trimedia ==Approach== The designers claim that the power and cost improvements come by adapting a DSP-like deeply-pipelined CPU to general-purpose code. The timing hazards from branches and memory access are said to be handled using speculative execution, pipelining and other late-binding but statically-scheduled logic. The claimed improvements in power and area are said to come from eliminating the dynamic optimization hardware: register-renaming, out-of-order execution hazard management and dynamic cache optimization. Therefore, the Mill architecture is designed as a compiler target for highly-optimizing compilers. The overall plan is to substitute static optimization at compile-time for hardware optimization at run time. To this end, each Mill CPU is designed to have timing and memory-access behavior that is predictable to single cycle times. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Mill CPU Architecture」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.